| Protocol | Use Case | |----------|-----------| | | Legacy I/O, GPUs, accelerators, SSDs | | CXL (v2.0/v3.0) | Cache-coherent memory expansion, memory pooling, accelerators | | Streaming | Raw data streams, non-coherent custom IP, streaming interfaces |
1. Executive Summary UCIe (Universal Chiplet Interconnect Express) is an open industry standard for die-to-die (D2D) interconnect and serial bus. It defines the physical layer, protocol stack, and compliance rules to enable heterogeneous chiplets (from different vendors, fabs, and process nodes) to interoperate seamlessly within a single advanced package. ucie spec
UCIe 2.0 (released August 2024, backward compatible with 1.0/1.1). This guide covers both. | Protocol | Use Case | |----------|-----------| |
As Moore’s Law slows, chiplet-based disaggregated System-on-Chips (SoCs) offer the path to higher performance, yield, and reusability. UCIe provides the "glue" to mix compute, memory, I/O, and analog chiplets from multiple sources. UCIe 2
| Protocol | Use Case | |----------|-----------| | | Legacy I/O, GPUs, accelerators, SSDs | | CXL (v2.0/v3.0) | Cache-coherent memory expansion, memory pooling, accelerators | | Streaming | Raw data streams, non-coherent custom IP, streaming interfaces |
1. Executive Summary UCIe (Universal Chiplet Interconnect Express) is an open industry standard for die-to-die (D2D) interconnect and serial bus. It defines the physical layer, protocol stack, and compliance rules to enable heterogeneous chiplets (from different vendors, fabs, and process nodes) to interoperate seamlessly within a single advanced package.
UCIe 2.0 (released August 2024, backward compatible with 1.0/1.1). This guide covers both.
As Moore’s Law slows, chiplet-based disaggregated System-on-Chips (SoCs) offer the path to higher performance, yield, and reusability. UCIe provides the "glue" to mix compute, memory, I/O, and analog chiplets from multiple sources.
