Verilog Frequency Divider -

module clk_enable_div8 ( input clk, rst_n, output reg clk_en ); reg [2:0] count; always @(posedge clk or negedge rst_n) begin if (!rst_n) count <= 0; else count <= (count == 7) ? 0 : count + 1; end assign clk_en = (count == 7); // one cycle wide pulse endmodule Then downstream modules use:

module div_by_3 ( input clk, rst_n, output reg clk_out ); reg [1:0] count; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin count <= 0; clk_out <= 0; end else begin if (count == 2) begin // 0,1,2 -> 3 cycles count <= 0; clk_out <= ~clk_out; end else begin count <= count + 1; end end end endmodule verilog frequency divider

module prog_divider #(parameter WIDTH=16) ( input clk, rst_n, input [WIDTH-1:0] divisor, // N value output reg clk_out ); reg [WIDTH-1:0] count; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin count <= 0; clk_out <= 0; end else begin if (count == divisor - 1) begin count <= 0; clk_out <= ~clk_out; end else begin count <= count + 1; end end end endmodule module clk_enable_div8 ( input clk, rst_n, output reg

module div_by_8_even ( input clk, input rst_n, output reg clk_out ); reg [1:0] count; // 2 bits for N/2 = 4 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin count <= 0; clk_out <= 0; end else begin if (count == 3) begin // N/2 - 1 count <= 0; clk_out <= ~clk_out; end else begin count <= count + 1; end end end endmodule Odd division (e.g., divide-by-3, 5, 7) is more complex because ( N/2 ) is fractional. A common method uses two counters : one triggered on the positive edge, the other on the negative edge, and the outputs are ORed or ANDed to reconstruct a near-50% duty cycle. Caveat: The divisor value must be ≥ 2

Caveat: The divisor value must be ≥ 2 and stable during operation. For very high input frequencies (e.g., 500 MHz in an ASIC), counter propagation delay may limit performance. Use synchronous prescalers with low-bit ripple counters or Johnson counters.